Unrestricted.2016-11-142011-02-182016-11-142008-08http://hdl.handle.net/2346/20038This dissertation presents several algorithmic and hardware design improvements to some of the recently proposed works using Markov sources for the scan built-in-test architecture. The first improvement is the use of the total probability rule and on-chip quantized probabilities to compute the sampling probability of the deterministic test cubes. Test cubes with low sampling probability are excluded from the final test set used to compute the transition probabilities. The second improvement is the use of new technique called dynamic transition selection, which combines transition inversion and transition fixing to produce test sequences. The third improvement is a new hardware design of the Markov source. Automatic Test Pattern Generator (ATPG) and fault simulator (HOPE) academic tools are used for generating deterministic test cubes and fault simulation, respectively. Espresso is used for logic minimization. The Sequential circiuit Synthesis tool (SIS) is used to map the synthesized design into a generic nand-nor library. Gate Equivalent (GE) count method [18] that reflects a static Complementary Metal Oxide Semiconductor (CMOS) technology: 0.5 GE for an inverter or a transmission multiplexer, (0.5)(n) GE’s for an n-input nand or nor, and (2.5)(n-1) GE’s for an n-input eXclusive-or (XOR) is used. The 5 larger International Symposium on Circuits and Systems (ISCAS89) benchmark circuits are tested using the new test pattern generator. The new test pattern generator achieves complete coverage of the stuck-at faults at signficantly reduced test length, with a modest increase in the gate count.application/pdfengBuilt in self test (BIST)System on a chip (SOC)Markov sourceTestingDissertation