Touba, Nur A.For modern logic circuits, circuit reliability is an important design consideration. Ionizing radiation from high-energy neutrons and alpha particles can cause a single-event upset (SEU) that may cause a bit flip in some latch or memory element thereby altering the state of the system resulting in a soft error. As process technology scales well below 100 nanometers, the higher operating frequencies, lower voltage levels, and smaller noise margins make integrated circuits increasingly susceptible to SEUs resulting in a dramatic increase in soft errors. In this dissertation, a non-intrusive technique is presented to detect soft errors in multilevel combinational logic circuit with minimal overhead. Another low cost error correcting code based technique is presented to detect and correct the most likely soft errors in memory. This technique is then extended to design a low cost unequal error protection code which can protect data residing in a router buffer effectively. The dissertation also contains a fast algorithm to accurately estimate signal probabilities of circuit lines. This algorithm can be used to estimate soft error rates in a logic circuit. Finally, the dissertation also includes a low cost test data compression technique to reduce the deterministic test data to be stored on tester during off-line testing of a circuit.1663861752008-08-282008-08-282007http://hdl.handle.net/2152/3034textelectronicengCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.Integrated circuits--ReliabilityThesis