Modeling and defect analysis of step and flash imprint lithography and photolithography



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In 1960's Gordon Moore predicted that the increase in the number of components in integrated circuits would exponentially decrease the relative manufacturing cost per component with time. The semiconductor industry has managed to keep that pace for nearly 45 years and one of the main contributors to this phenomenal improvement in technology is advancement in the field of lithography. However, the technical challenges ahead are severe and the future roadmap laid by the International Technology Roadmap for Semiconductors looks mostly red (i.e. no solution has been found to specific problem). There are efforts in the industry and academia directed toward development of newer, alternative lithographic techniques. Step and Flash Imprint Lithography (SFIL) has recently emerged as one of the most promising alternatives, capable of producing high resolution patterns. While it has numerous advantages over conventional photolithography, several engineering challenges must be overcome to eliminate defects due to the nature of contact imprinting if SFIL is to be a viable alternative technique for manufacturing tomorrow's integrated circuits. The complete filling of template features is vital in order for the SFIL imprint process to truly replicate the template features. The feature filling phenomena for SFIL was analyzed by studying diffusion of a gas, entrapped in the features, through liquid imprint resist. A simulation of the dynamics of feature filling for different pattern configurations and process conditions during the SFIL imprint step is presented. Simulations show that initial filling is pressure-controlled and very rapid; while the rest of the feature filling is diffusion-controlled, but fast enough that diffusion of entrapped gas is not a cause for non-filling of features. A theory describing pinning of an air-liquid interface at the feature edge of a template during the SFIL imprint step was developed, which shows that pinning is the main cause of non-filling of features. Pinning occurs when the pressure at the air-liquid interface reaches the pressure of the bulk liquid. At this condition, there is no pressure gradient or driving force to move the liquid and fill the feature. The effect of several parameters on pinning was examined. A SFIL process window was established and template modifications are proposed that minimize the pinning at the feature edge while still preventing any extrusion along the mesa (pattern containing area on the template) edge. Part of semiconductor manufacturing community believes that optical lithography has the capability to drive this industry further and is committed to the continuous improvement of current optical patterning approaches. Some of the major challenges with shrinking critical dimensions (CDs) in coming years are the control of line-edge roughness (LER) and other related defects. The current CDs are such that the presence or absence of even a single polymer molecule can have a considerable impact on LER. Therefore molecular level understanding of each step in the patterning process is required. Computer simulations are a cost-effective approach to explore the huge process space. Mesoscale modeling is one promising approach to simulations because it captures the stochastic phenomena at a molecular level within reasonable computational time. The modeling and simulation of the post-exposure bake (PEB) and the photoresist dissolution steps are presented. The new simulator enables efficient exploration of the statistical excursions that lead to LER and the formation of insoluble residues during the dissolution process. The relative contributions of the PEB and the dissolution step to the LER have also been examined in the low/high frequency domain. The simulations were also used to assess the commonly proposed measures to reduce LER. The goal of the work was to achieve quantification of the effect of changes in resist composition, developer concentration, and process variables on LER and the associated defectivity.