Design And Study Of Phase Locked Loop For Space Applications In Sub-micron Cmos Technology
This work proposes a successful design of a radiation hard phase locked loop (PLL) using Silicon-on-Sapphire CMOS (SOS) technology for space applications. A fully self-bias radiation hard PLL providing frequency of 2.5 GHz has been designed for the first time on SOS technology. SOS technology is used to provide radiation hardness from Single Event Effects (SEE), an improvement over the use of commercially available bulk CMOS process. Innovative designs of VCO implemented in the PLL, architectural modifications in the use of buffers, bias stages, asynchronous dividers and optimization of fully self-bias design provide hardness from Total Ionization Dose (TID). Self-bias design, which provides noise immunity from external (Substrate and Supply) noises by incorporating symmetric load in the VCO and a biasing feedback loop, produces high internal noise, which is critical for the performance of the VCO. Thus, a novel VCO design is designed, which gives several dB of less phase noise than the typical symmetric load VCO used in the self-bias PLL for the same frequency of oscillation. TID effects degrade the phase noise of the VCO. Thus, lowering the phase noise of the VCO as much as possible is important under radiation environment. The novelty introduced in the differential stages of the VCO cancels common mode noise (by clamped load), reduces corner frequency of 1/f noise (by cross-coupled load) and reduces supply/substrate noise (by symmetric load). The substrate conduction of noise is also restricted by the use of the SOS technology. TID effects can shift the operating region of the VCO to such a place where it may not work at all. Therefore, a huge tuning range of VCO is required, so that it can regain its proper functionality after it is displaced from its operating region. It is very critical for the proper functioning of the PLL. The new load design for the VCO provides a large tuning range. This was made possible by the use of cross-coupled load, which increases the amount of output voltage swing at certain controlling voltages. In addition, the use of clamped load in the load structure of the VCO provides a linear gain for the VCO, which in turn increases the tuning range.Analytical expressions have been derived for phase noise of the new VCO and mathematical model has been derived for functioning of the PLL. The analytical expression is very important, as it will show the effects of different design parameters on the phase noise of the VCO.Each block of the PLL has been developed individually for successful implementation in the radiation environment. Multiple stages of level shifters ("differential to single ended blocks") have been used between the VCO and the frequency dividers to enhance the signal levels of the produced oscillation. This is important for the next stages, which are the dividers, to work properly in the radiation environment. This implementation provides robustness against radiation effects. Symmetric dividers are preferred for implementing frequency dividers in PLL, as they reduce "clock to Q" delay. However, in radiation environment they tend to fail, thus, frequency division in this PLL is implemented by asynchronous dividers. Five blocks of individual "divided by two" stages have been used for simplicity and robustness. The phase frequency divider (PFD) used is specially designed to be TID tolerant as the "Voltage-Transfer-Curve" of the individual blocks in the PFD do not move much away from the fresh implementations under radiation effects. Two self-bias stages are used. The self-bias stages provide controlling voltage and bias voltage for the current controlling stages in the VCO. This new arrangement is simple and provides stable controlling voltage to the VCO. This is very critical, as in case of any strong SEE hit at the output of the charge pump the disturbances will be dampened because of the isolation produced by the second self-bias stage.In order to reduce the overall phase noise of the PLL capacitors are used at the controlling voltage node and the bias voltage node of the VCO. These capacitors are at least one tenth in value of the loop filter capacitance. The simulation results for the phase noise of the different VCO designs have been presented. The plot for comparison has been presented, which shows that our VCO performs better. In addition, the plots for the functioning of each block have been presented. This is true for individual blocks and the PLL as a whole as well. The blocks required to build the self-bias PLL have been designed in schematic and drawn in layout. They have been designed to withstand radiation effects for all the process corner, temperature and voltage variations. The blocks have been simulated in schematic and layout to verify their performances. These exercises were carried out, first with fresh device model files and then with irradiated device model files. The PLL has been successfully simulated for all the process (SS/FF/TT/SF/FS), temperature (-40ºC to +80ºC) and voltage variations. The PLL is robust and performs successfully in both fresh and radiation environment. The PLL has been simulated in Cadence-SpectreRF for schematic and layout simulations for fresh and radiation environment cases. The PLL achieves 2.5 GHz of output frequency. The VCO achieves a phase noise of -90dBc/Hz at an offset of 1 MHz. The VCO achieves tuning range of more than 2.5 GHz. The PLL locks in less than 600nS for the radiation hard design. The overall jitter is less than 12 pS for the radiation environment.