A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing



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Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. As NoC size increases with core count in future many-core chips, NoC router efficiency is critical to achieving performance scaling. This thesis explores router microarchitectures which leverage traffic pattern biases and imbalances to reduce latency and improve network throughput. It introduces STORM ? Simple Traffic-Optimized Router Microacrchitecture ? a new, low-latency, fair, high-throughput NoC router design, customized for the traffic seen in a two-dimensional mesh network employing dimension-order routing. Compared to a baseline NoC router with equivalent buffer resources, STORM offers single cycle operation and reduced cycle time (up to 17% less than the baseline on 45nmCMOS), with less area and power consumption when synthesized at the same clock frequency as the baseline. This design yields a higher overall network saturation throughput (up to 14.6% higher than the baseline) in an 8x8 2D mesh network for uniform random traffic. STORM also reduces packet latencies under realistic workloads by 41% on average.