Lithography variability driven cell characterization and layout optimization for manufacturability



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Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed.