Advanced III-V MOSFET

Date

2016-05

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

As scaling of silicon-based CMOS devices approaches its end, there is an ever increasing interest in high mobility materials. Among potential candidates for future CMOS devices, III-V materials are the most promising option due to their superior carrier transport properties. Despite their attractive material properties, they face several critical challenges that need to be resolved. The main limitation in III-V MOSFETs is lack of a good native oxide. Recently, devices utilizing a gate stack formed with high-κ and metal gate electrode are being explored for EOT scaling. Compared to Si MOSFETs, the surfaces of III-V channel materials are prone to deteriorate, resulting in degradation threshold voltage control, subthreshold characteristics, and overall device performance. The purpose of this dissertation is to address improvement of surface characteristics of III-V materials, especially, InGaAs. First of all, beryllium oxide (BeO) is considered as interface passivation layer for InGaAs MOSFETs. In order to apply BeO onto InGaAs, the chemical and mechanical properties are first studied. Liquid BeO precursor is never used in ALD systems. The chemical properties of ALD BeO film are revealed from AES, XPS, NRA, RBS, and REELS. Using nano-indentation, the mechanical characteristics of ALD BeO are investigated. The second part of the study focuses on the application of ALD BeO to InGaAs MOSFETs. The surface channel MOSFET is employed to understand BeO dielectric with III-V channel. The quantum well (QW) structure is known to withstand InGaAs intrinsic material properties from a device point of view. ALD BeO is applied to QW InGaAs MOSFETs as an interface passivation layer below HfO2. The impact of ALD BeO application for interface passivation is presented using the improvement in device characteristics, for example, drive current (ION), low leakage current (IOFF), effective mobility (μeff), and interface trap density (Dit). The third and final part are about process research for InGaAs surface quality. III-V channel materials are inherent to create notorious native oxide that needs to be treated before the fabrication process. In order to protect pristine III-V surface, in-situ Ar treatment is studied and used before high-κ deposition. In addition, deuterium (D2) high-pressure annealing is considered to passivate III-V interface with high-κ. To demonstrate the efficacy of these treatment processes, InGaAs MOSCAPs are fabricated, and capacitance characteristics are analyzed and compared. The C-V hysteresis and multi-frequency C-V are measured, and the interface trap density (Dit) is extracted using the C-V result.

Description

Citation