Dynamic Control of Serial-batch Processing Systems
Abstract
This research explores how near-future information can be used to strategically control a batch processor in a serial-batch processor system setting. Specifically, improved control is attempted by using the upstream serial processor to provide near-future arrival information to the batch processor and further meet the re-sequencing requests to shorten critical products? arrival times to the batch processor. The objective of the research is to reduce mean cycle time and mean tardiness of the products being processed by the serial-batch processor system. This research first examines how mean cycle time performance of the batch processor can be improved by an upstream re-sequencing approach. A control strategy is developed by combining a look-ahead control approach with an upstream re-sequencing approach and is then compared with benchmark strategies through simulation. The experimental results indicate that the new control strategy effectively improves mean cycle time performance of the serial-batch processor system, especially when the number of product types is large and batch processor traffic intensity is low or medium. These conditions are often observed in typical semiconductor manufacturing environments. Next, the use of near-future information and an upstream re-sequencing approach is investigated for improving the mean tardiness performance of the serial-batch processor system. Two control strategies are devised and compared with the benchmark strategies through simulation. The experimental results show that the proposed control strategies improve the mean tardiness performance of the serial-batch processor system. Finally, the look-ahead control approaches that focus on mean cycle time and mean tardiness performances of the serial-batch processor system are embedded under a new control strategy that focuses on both performance measures simultaneously. It is demonstrated that look-ahead batching can be effectively used as a tool for controlling batch processors when multiple performance measures exist.