Multi-generational test plan generation and execution in advanced mixed signal controllers

Most integrated circuits are evolutionary. This is especially true in the realm of system-on-a-chip (SoC) devices that combine multiple functions monolithically. Electronic systems that begin life as an entire printed circuit board often see smaller and smaller chip counts as designs mature. In some cases, functions will be combined into multichip modules that co-locate separate integrated circuits in a single package to provide additional levels of signal integrity and achieve cost reductions. This process continues through stages that culminate in the monolithic integration of these separate chips. The requirement to differentiate similar functions for different customers and applications results in families of SoC’s with similar but not identical capabilities. As parametric and functional testing become larger and larger contributors to total cost, avoiding duplication of effort is a key factor in maintaining competitive position and market share. The strategies involved in achieving economies of scale that can be realized by recognizing the similarities between family members while still providing for differentiation where required is a subject of great interest currently. This work traces the development of test capability in such a family through several generations. An approach that utilizes a motherboard to take advantage of the similarities between family members and is combined with specialized hardware realized in a series of daughter boards, and differentiated software as well is described through several design iterations. Debugging both hardware and software while looking for ways to streamline testing and further reduce test time and cost is detailed. The result is a cost effective approach to advanced device testing that does not compromise performance and provides for acceptable levels of fault coverage.