Analog hardware description language for a radio frequency system
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The purpose of this thesis is to investigate the possibility of using AHLDs for applications in implementing a top-down design methodology. A good example of this is an electrical system, specifically a receiver in an RF system. This particular circuit was chosen because it is a good representation of a circuit that contains an adequate amount of circuitry with enough complexity for a first attempt to develop a behavioral model of a system level circuit. Verilog-AMS was used to simulate the RF receiver circuit and the Cadence design system, especially SpectreS along with Analog Artist, was used to implement the Verilog-AMS code. This is capable of behavioral modeling as well as the total control of the conventional simulation models. In order to simulate both schematics and Verilog-AMS blocks, general purpose-building blocks are used as in digital simulation. Cell libraries are used in digital hardware description languages. For this analogy, broadband amplifiers are chosen. In this thesis the circuit simulation for a down converter in a receiver circuit by the conventional and the Verilog-AMS were accomplished and compared. The remainder of this thesis is organized as follows. Chapter II reviews the background of the Analog Hardware Description Language, especially Verilog-AMS including a brief history of the earlier applications. As the application of this thesis, a down converter is discussed in Chapter III. In this chapter the theory, background, and a brief history are discussed. Also the simulation results using SpectreS are shown. Next Chapter IV discusses the results using Verilog-AMS. Various simulation results such as gain, noise, and IIP3 are shown for several sub-blocks. These results are compared to the results in chapter III. Chapter V summarizes the results and contains a discussion.