Implementation of a probabilistic model for predicting power consumption of a field programmable gate array

As configurable computing devices like FPGAs gain popularity as application-specific computing solutions, the special problems presented by these devices must be considered. For example, the power consumed by the FPGA can be heavily dependent upon the dynamic nature of the input data. In addition, the routing resources that allow FPGAs to be reconfigured can be a significant source of power consumption. Because changes in the device's configuration can affect both of these issues, the opportunity exists to optimize the utilization of the FPGA's resources before the device is actually configured. A fast method of modeling an FPGA's power consumption would be an important tool to achieve this end.

This thesis explores the problem of modeling power within a reconfigurable device. A probabilistic method for modeling power consumption within an FPGA is presented. The implementation of this method is the basis of the developed power prediction simulator.