Transmitter and receiver circuits for digital free-space optical interconnect: design and simulation

Modem computer processors run at a speed of many GHz but the off-chip interface runs only at a speed of a few hundred MHz. A key reason for this difference, and a problem for computing in general, is that the interface connection speeds are not able to keep up with the increase in processor speeds. This is due to design issues associated with electrical wires and their underlying physical properties. Due to the capacity limitations of electrical wires, all long distance communication is now done via optics. Optics has many features, beyond those exploited in long distance fiber communications, which make it interesting for connections at short distance, including dense optical interconnections directly to silicon integrated circuit chips. Optical interconnects to chips have been studied for a long time. This study started with the seminal paper by Goodman [1]. Since then, many authors have addressed the benefits and limitations of optical interconnects ([2][3][4][5][6][7][8][9][10][11]).

Development of CMOS transmitter and receiver circuits is required for integrating digital free space optical interconnects (FSOI) with the mainstream VLSI computing system. These circuits are the interface between on-chip digital signals and the off-chip optical signals, and thus their design and optimization is very important. In the analog regime, their noise, frequency response and stability are taken as important design criteria. In the digital regime, they must be fast, small, low power and reliable. Meeting these design criteria makes the design more complicated.

We will first examine the analysis and design of transmitter and receiver circuits for FSOI. Then, we will optimize the receiver circuit for various design parameters. Then we will design the transmitter circuit based on the receiver circuit requirements. We will finally conclude by providing the simulation results of the total link.