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dc.rights.availabilityUnrestricted.
dc.creatorLiu, Qi
dc.date.accessioned2016-11-14T23:10:29Z
dc.date.available2011-02-19T00:26:55Z
dc.date.available2016-11-14T23:10:29Z
dc.date.issued1999-05
dc.identifier.urihttp://hdl.handle.net/2346/21613en_US
dc.description.abstractA 3-bit recoding algorithm is used to implement a parallel multiplier in two's complement. The circuits at gate level for implementing 8 x 8-bit multiplier are presented. To obtain highest speed, (1) carry skip adders combined with carry select adders are adopted to implement two's complement multiplier, (2) carry save adders combined with carry select adders are used to add partial products. An 8x8-bit multiplier was implemented physically with 1.2^m CMOS SCN (Scaleable N-well) technology using Tanner L-Edit CMOS layout tool. The area of the chip (not including pads frame) is 1 mm . The chip has been fabricated and tested. From the chip test, the execution time is less than 5.7ns. A 16x16-bit multiplier implemented with 8x8-bit multiplier cells using Pspice software tool was also presented. The execution time of the 16x16-bit multiplier is about 1.5 times that of the 8x 8-bit multiplier from the Pspice simulation.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.subjectMultipliersen_US
dc.subjectIntegrated circuitsen_US
dc.titleDesign of multiplier and its VLSI implementation
dc.typeThesis


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