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dc.degree.departmentElectrical and Computer Engineeringen_US
dc.rights.availabilityUnrestricted.
dc.creatorFavela, Eduardo
dc.date.accessioned2016-11-14T23:09:48Z
dc.date.available2011-02-18T23:57:21Z
dc.date.available2016-11-14T23:09:48Z
dc.date.issued2001-12
dc.identifier.urihttp://hdl.handle.net/2346/20828en_US
dc.description.abstractThe focus of this paper is to investigate the boundary-scan benefits of VLSI testing at the device level. As advances in semiconductor technology allow for faster and more complex ICs, the physical dimensions of devices are also decreasing as well. The smaller dimensions limit physical access of test points within a device under test, which require the use of test strategies to address these testing issues. In addition, the time required to test a device increases as the complexity and density increases. Therefore, there is an endless search for solutions to testing issues and the reduction of the high costs associated with testing the device. Boundary-scan was designed to address the testing issues at the board. However, boundary-scan is exploited to facilitate testing at the device level addressing the concerns of In-Circuit testing. The benefits of boundary-scan extend from the device level to the board/system level to the field level.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherTexas Tech Universityen_US
dc.subjectBoundary scan testingen_US
dc.subjectIntegrated circuits -Very large scale integrationen_US
dc.titleBenefits of VLSI boundary-scan testing
dc.typeThesis


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