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dc.contributor.committeeChairNutter, Brian
dc.contributor.committeeMemberGale, Richard O.
dc.degree.departmentElectrical and Computer Engineering
dc.rights.availabilityUnrestricted.
dc.creatorReich, Jonathan R.
dc.date.accessioned2016-11-14T23:29:30Z
dc.date.available2012-06-01T17:48:32Z
dc.date.available2016-11-14T23:29:30Z
dc.date.issued2008-12
dc.identifier.urihttp://hdl.handle.net/2346/17758
dc.description.abstractAs semiconductor technology advances, the functionality and complexity of microprocessors increase. Establishing proper test methods is an important electrical characteristic of testing a DUT (Device Under Test). With a large scale microprocessor’s pin count exceeding one thousand, abstract methods must be used to insure proper test integration between the tester and DUT. Because the majority of tests performed on high-end microprocessors are complex and sensitive to noise, it is becoming more important that quality electrical connections are being made. The purpose of this thesis is to tighten CRes test limits so solder ball integrity can be verified to eliminate a test insertion from the production test flow. Previous CRes limits were relaxed due to complications while testing CRes. These complications and solutions will be addressed in this thesis. This thesis will describe methods of testing and optimization to enhance yield while testing contact resistance (CRes) on large pin count SUN Niagara 2 and Victoria Falls microprocessors using a LTX Fusion VX4/VX5 tester. This thesis will also discuss test methods to reduce mechanical error associated between the tester and the DUT.
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.subjectYield
dc.subjectEnhancement
dc.subjectContact resistance
dc.subjectOptimization
dc.titleOptimization and yield enhancement for measuring contact resistance in large scale microprocessors
dc.typeThesis


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