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Federated Electronic Theses and Dissertations
Texas Tech University
Top-level verilog model for a serial transceiver
Top-level verilog model for a serial transceiver
Date
2001-12
Authors
Tummala, Udaykaran Reddy
Journal Title
Journal ISSN
Volume Title
Publisher
Texas Tech University
Abstract
Not available
Description
Keywords
Integrated circuits -- Computer simulation
,
Integrated circuits -- Verification
,
Computer hardware description languages
Citation
URI
http://hdl.handle.net/2346/16100
Collections
Texas Tech University
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