Design of an ASIC chip for a Controller Area Network (CAN) protocol controller

This thesis describes the design, simulation and ASIC implementation of a protocol controller for the Controller Area Network (CAN) 2.0A multi-master serial communication protocol. The CAN Controller designed will function as the interface between an application and the actual CAN bus. The RTL based design is implemented using Verilog HDL. Physical realizations of the design are obtained with Magma tools. Logic Equivalence is verified using Cadence Verplex. Simulations are made at each level to verify the implementations. The system was implemented in TSMC 0.13ìm CMOS six metal process.