Effect of downscaling copper interconnects on the microstructure revealed by high resolution tem orientation mapping

The scaling required to accommodate faster chip performance in microelectronic devices has necessitated a reduction in the dimensions of copper interconnects at the back end of the line. The constant downscaling of copper interconnects has resulted in changes to the microstructure, and these variations are known to impact electrical resistivity and reliability issues in interconnects. In this work, a novel electron diffraction technique called Diffraction Scanning Transmission Electron Microscopy (D-STEM) has been developed and coupled with precession electron microscopy to obtain quantitative local texture information in damascene copper lines (1.8 \mu m to 70 nm in width) with a spatial resolution of less than 5 nm. Misorientation and trace analysis has been performed to investigate the the grain boundary distribution in these lines.

The results reveal strong variations in texture and grain boundary distribution of the copper lines upon downscaling. 1.8 \mu m wide lines exhibit strong <111> normal texture and comprise large bamboo-type grains. Upon downscaling to 180 nm, a {111} <110> biaxial texture has been observed. In contrast, narrower lines of widths 120 nm and 70 nm reveal sidewall growth of {111} grains and a dominant <110> normal texture. The fraction of coherent twin boundaries also reduces with decreasing line width. The microstructure changes from bamboo-type in wider lines to one comprising clusters of small grains separated by high angle boundaries in the vicinity of large grains. The evolution of such a microstructure has been discussed in terms of overall energy minimization and dimensional constraints. Finite element analysis has been performed to correlate misorientations between grains and local thermal stresses associated with stress migration. Effect of variations in the copper interconnect microstructure on electromigration flux divergence has also been discussed.