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dc.contributor.advisorOrshansky, Michaelen
dc.contributor.committeeMemberMcdermott, Marken
dc.creatorLok, Mario Chichunen
dc.date.accessioned2010-10-26T21:09:38Zen
dc.date.accessioned2010-10-26T21:09:44Zen
dc.date.accessioned2017-05-11T22:20:29Z
dc.date.available2010-10-26T21:09:38Zen
dc.date.available2010-10-26T21:09:44Zen
dc.date.available2017-05-11T22:20:29Z
dc.date.issued2010-05en
dc.date.submittedMay 2010en
dc.identifier.urihttp://hdl.handle.net/2152/ETD-UT-2010-05-1167en
dc.descriptiontexten
dc.description.abstractIn many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield.en
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.subjectLow power designen
dc.subjectAdaptive circuiten
dc.subjectStatistical sizingen
dc.subjectTunable circuiten
dc.subjectAdaptable optimizationen
dc.titleProcess variation aware low power buffer designen
dc.type.genrethesisen
dc.date.updated2010-10-26T21:09:44Zen


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