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dc.contributor.advisorAbraham, Jacob A.en
dc.identifier.oclc56208151en
dc.creatorKrishnamachary, Arunen
dc.date.accessioned2008-08-28T21:32:30Zen
dc.date.available2008-08-28T21:32:30Zen
dc.date.issued2003en
dc.identifierb56858966en
dc.identifier.urihttp://hdl.handle.net/2152/714en
dc.descriptiontexten
dc.description.abstractThe rapidly evolving process technologies and device complexity that have fueled the exponential growth in the performance of microprocessors have made the manufacturing test of these devices a hard problem. In addition to making the detection of defects modeled by the classical fault models like the stuck-at and the transition fault model more complex, these process technologies have resulted in additional types of defects (like the resistive opens, defects due to the process parameter variations and crosstalk defects) becoming more prominent. The requirement for an effective delay test framework which involves an effective fault model, optimized test generation procedure and efficient test application has become even more urgent in the current scenario. This framework also needs to address the issues with yield and complexity (due to the large number of faults) that are associated with a delay test strategy. In this dissertation, we provide a strategy to help address many of the issues outlined above. An improved delay fault model is first proposed which enables better detection of resistive open defects and also yields a good oppurtunistic coverage of defects due to process parameter variations. This is coupled with an optimized test generation strategy, which facilitates efficient delay test generation under the fault model. A fault collapsing technique helps reduce the number of faults that need to be targeted. To improve the yield of a scan based test application, a technique is provided to identify the functional sensitizability of paths across multiple latch boundaries, and the effect of this strategy on yield is then calculated. Finally a technique to enable use of ATPG to evaluate the chip level sensitizability of paths which enables the use of tighter timing bounds in chips is presented.
dc.format.mediumelectronicen
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshMicroprocessors--Testingen
dc.titleTest generation for realistic defectsen
dc.description.departmentElectrical and Computer Engineeringen
dc.type.genreThesisen
dc.identifier.proqst3119626en


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