Thermal-mechanical stress measurement and analysis in three dimensional interconnect structures with Raman spectroscopy

Three-dimensional (3-D) integration as an effective method to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through Silicon Via) is essential for 3D silicon integration and 3D IC integration. TSV are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the process, and they have caused serious concerns regarding the thermal-mechanical reliability. In this thesis, we mainly used Micro- Raman spectroscopy characterized the thermal-mechanical stress distribution at both near surface and cross-section of Si around TSV. First we use the conventional Raman, to measure the linear combination of in-plane stress components. The local distribution of near-surface stress in Si has been measured, in comparison with stress analysis of the TSV structure based on a semi-analytic approach and finite element analysis. The effects of residual stress in surface oxide layer and the interaction of stress field of neighboring TSVs are evaluated experimentally. Second, the limitation of conventional Raman measurement is discussed, and two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately by taking advantages of different laser polarization configuration. The top view Raman measurements utilize so called "High NA effect" to obtain additional information, and can resolve all 3 normal stress components near the top surface of silicon. From the cross-section Raman measurements, the in-plane stress distribution in Silicon on the cross-section can be determined with reasonable assumption based on FEA simulation. There shows good agreements between FEA simulation and experimental data in general.