A fractional N frequency synthesizer for an adaptive network backplane serial communication system
Rangan, Giri N. K.
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An architecture and design of a Phase Locked Loop based frequency synthesizer is developed in this dissertation. Using multiple phases generated by a ring oscillator, this synthesizer is able to generate non-integer multiples of the incoming, high quality clock signal. The design is done for a nominal target frequency of 3.125 GHz for application in a serial communication system such as a network backplane. Using a fully differential design, the architecture is able to achieve the stringent timing jitter requirements of a network backplane system. Advancements in the content and the coverage of the Internet have tremendously increased the need for high speed data transport over very long and very short distances. The long distance bandwidth and speed requirements have been addressed by the use of optical links. The shorter distances, such as serial communications in a network backplane are still in the realm of copper lines drawn on printed circuit boards. Thus the medium of communication places design constraints on the electronic devices operating on either side of the medium. As symbol frequencies approach 3.125 GHz and beyond, architectural modifications must be made to alleviate the channel effects. This dissertation presents a phase locked loop for a network backplane system application where the two transceivers can communicate with each other to determine a particular line code that they will use for the most optimal communication between them. The selection of the line code determines the symbol rate and in turn the transmit clock frequency. A particular line code may be chosen such that a non-integer multiple of a low frequency input clock is required. The incoming clock is usually fixed at standard frequencies like 312.5 or 625 MHz to operate the parallel data path. It would then be beneficial to have a fractional-N frequency synthesizer which can generate the necessary fractional frequency multiples. The synthesizer presented in this research work is designed in a standard 0.13 µm CMOS technology with a 1.5 V power supply. It dissipates 112 mW of power and occupies an estimated silicon area of 0.2 sq. mm. The nominal peak to peak jitter of this design is approximately 43.7 ps and the maximum peak to peak jitter is 48 ps.