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dc.contributor.advisorHo, P. S.en
dc.identifier.oclc70915310en
dc.creatorLu, Xiaen
dc.date.accessioned2008-08-28T22:40:47Zen
dc.date.accessioned2017-05-11T22:17:05Z
dc.date.available2008-08-28T22:40:47Zen
dc.date.available2017-05-11T22:17:05Z
dc.date.issued2005en
dc.identifierb61114303en
dc.identifier.urihttp://hdl.handle.net/2152/2273en
dc.descriptiontexten
dc.description.abstractInterconnect scaling has given rise to serious reliability concerns under the impact of low k integration, new processes, and shrinking dimensions. This dissertation attempts to explore the scaling effects on the two main reliability issues in Cu metallization: electromigration (EM) and stress migration. The EM lifetime characteristics were studied on dual damascene Cu/low k interconnect structures for different low k dielectrics with scaling of the metal line width and barrier thickness. A Monte Carlo simulation was used to deduce the statistical parameters for intrinsic EM failures and extrinsic early failures. It was found that line width scaling, when accompanied by corresponding via size scaling, caused an almost linear decrease in the intrinsic EM lifetime, indicating the presence of a critical failure void volume, which depends on line geometry of the cathode end. FIB/SEM and TEM analyses revealed that copper out-diffusion due to defective barrier coverage caused lifetime degradation and line shorting. The threshold current densitylength (jL)c product was also studied on test structures with three different barrier thicknesses, in both electron flow directions, and processed with different processes. A 3- D Finite Element Analysis (FEA) was employed to investigate the confinement effect through examining the effective bulk modulus B. The change from oxide to low k dielectrics considerably reduced B as well as the (jL)c values. However, unlike the effective bulk modulus B, which scaled with the barrier thickness, the (jL)c product did not demonstrate a clear trend. This can be attributed to the decreasing experimental accuracy with a much reduced (jL)c value and the small difference in the actual confinement due to the barrier thickness variation. Any process-related void formation at an unfavorable location can also significantly reduce the critical failure void volume and the (jL)c values. Stress migration measurement was performed on Kelvin structures with different underlying metal-1 layer thicknesses and different Cu electroplating chemistries. A lower impurity level or a thinner metal layer thickness was found to degrade the stress migration performance. Microstructural characterization, thermal stress measurement, and 3-D FEA modeling were performed to interpret the observed stress migration results. And a possible failure mechanism was proposed.
dc.format.mediumelectronicen
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshElectrodiffusionen
dc.titleImpact of interconnect scaling on electromigration and stress migration reliabilityen
dc.description.departmentMaterials Science and Engineeringen
dc.type.genreThesisen


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