Process development, characterization, transient relaxation, and reliability study of HfO₂ and HfSi(x)O(y) gate oxide for 45nm technology and beyond

Silicon CMOS technology has been advancing along an exponential path of aggressively shrinking device dimensions, increasing density, increasing speed, and decreasing cost. Although providing huge benefits in microprocessor performances, advances in technology are accelerating the onset of causing enormous challenges in device integration and reliability. With device miniaturization, device design and process errors are shrinking, which in turn impact device characteristics and reliability. To keep pace with aggressive scaling, CMOS conventional SiO2 gate oxide are facing tremendous challenges in power consumption and reliability. Aggressive scaling of SiO2 pushed the technology down to the limit of direct tunneling regime, where the gate oxide leakage current increases exponentially as the thickness decreases. Thus the high ix performance is coming from sacrificing both static and dynamic power of the circuits. Scaling up to 65nm technology node, use of SiO2 and SiOxNy based dielectric barely met the ITRS roadmap. But keeping the same architecture with the same material we can’t meet the 45nm technology gate oxide thickness and leakage current requirements. Therefore high-k dielectrics, of which HfO2 and their silicates are most promising candidates, have attracted a great deal of attention recently. However, high-k dielectrics have also faced lots of integration challenges and issues that are needed to be resolved carefully before pushing it in production. For example, bulk charge trapping, interface states, degraded mobility, growth of interfacial layer, low crystallization temperature, dielectric phase separation, fermi pinning, soft optical phonon scattering, remote coulomb scattering, pre-existing traps are among those issues. In this research, process development, characterization and reliability study of HfO2 and its silicate have been performed. It has been observed that both nitrogen (N) and chlorine (Cl) have significant effect in improving the device performances. Incorporation of nitrogen by NH3 post-deposition anneal reduced EOT (effective oxide thickness), and improved device characteristics, like Id-Vg, Id-Vd characteristics, and mobility. On the other hand, surface nitridation using NH3 was found to be an effective way to aggressively scale down the EOT. Moreover, Cl treatment using precursor, HfCl4 pulse time variation in ALD (atomic layer deposition) HfO2, and using HCl as high-k post deposition rinsing element, both mobility and bias instabilities of high-k oxides could be improved. Reliability of Hf-based oxide could be improved by compositionally varying HfSixOy structure. Fabricating Hf-silicate with low composition of Si on top of Hf silicate with high composition of Si not only enhanced the device performance, but also improved the reliability characteristics. Furthermore, insertion of Si in the HfOxNy dielectric was found to be an effective way to improve device performance and reliability. At the end, a novel approach in understanding the breakdown mechanism of HfO2 has been proposed by stress-anneal experiments. It was found that accumulation of holes is primarily responsible for breakdown of HfO2 under substrate injection condition. An appropriate model has also been proposed along with supporting experimental data. Considering all of the process development, characterization and reliability studies made in this research, it can successfully be asserted that high-k gate oxide can be proposed as a viable and promising candidate for 45nm technology and beyond. But still careful attention need to be taken to resolve remaining intrinsic and extrinsic issues in high-k gate oxide.