New approaches and limits to test data compression for systems-on-chip

Recent advances in design technology have made it possible to build systems containing different types of components on the same chip. These complex systems-onchip (SoC) contain components that cover a wide range of functions and technologies from processors and other digital circuits in CMOS to DRAM to analog circuits. As a result, the testing of such complex SoCs has become an important and dif- ficult problem. This thesis investigates the use of test data compression methods to deal with the enormous amount of test data of complex SoCs. The first part of this thesis studies the use of an embedded processor present in the SoC to help in testing the other cores. Specifically, the focus is on the use of processor to perform test vector decompression in software. The next part of this thesis looks at methods for improving the compression of hardware based linear decompression techniques. The last part uses entropy theory to calculate the limits to test data compression.