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dc.contributorEntesari, Kamran
dc.creatorEschenko, Evan Lee
dc.date.accessioned2010-01-15T00:12:25Z
dc.date.accessioned2010-01-16T00:36:55Z
dc.date.accessioned2017-04-07T19:55:18Z
dc.date.available2010-01-15T00:12:25Z
dc.date.available2010-01-16T00:36:55Z
dc.date.available2017-04-07T19:55:18Z
dc.date.created2007-12
dc.date.issued2009-05-15
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2496
dc.description.abstractA low power implementation of a CMOS frequency synthesizer at 12 GHz is an important step to improve the efficiency of a wireless transceiver in this frequency band. Since synthesizers are often employed as reference frequency sources such as local oscillators for up or down-conversion in communications system, their design is especially important for high performance transceiver applications. CMOS PLLs operating at high frequencies consume large amounts of power for proper operation, making power efficiency a top priority in transciever implementation. In response, this thesis presents a low power phase and frequency detector with True Single Phase Clocking by employing the .18? TSMC process with a 1.8 V supply voltage. A conventional but extremely power efficient nano-watt charge pump is also implemented for additional power savings. Furthermore, a state of the art 16/17 prescaler using Current Mode Logic (CML) D-Flip Flops, CMOS inverters, and transmission gates has been optimized for maximum power savings. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in Transmission Gate Logic (TGL) to reduce the power consumption. To the best of my knowledge, this technique has never been used in a high frequency prescaler before.
dc.language.isoen_US
dc.subjectPrescaler
dc.titleA low power prescaler, phase frequency detector, and charge pump for a 12 ghz frequency synthesizer
dc.typeBook
dc.typeThesis


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