Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial
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This work introduces fundamental knowledge of EMI, and presents three basic features correlated to EMI susceptibility: nonlinear distortion, asymmetric slew rate (SR) and parasitic capacitance. Different existing EMI-resisting techniques are analyzed and compared to each other in terms of EMI-Induced input offset voltage and other important specifications such as current consumption. In this work, EMI-robust analog circuits are proposed, of which the architecture is based on source-buffered differential pair in the previous publications. The EMI performance of the proposed topologies has been verified within a test IC which was fabricated in NCSU 0.5um CMOS technology. Experimental results are presented when an EMI disturbance signal of 400mV and 800mV amplitude was injected at the input terminals, and compared with a conventional and an existing topology. The tested maximal EMI-induced input offset voltage corresponds to -222mV for the new structure, which is compared to -712mV for the conventional one and -368mV for the one using existing source-buffered technique in literature. Furthermore the overall performances of the circuits such as current consumption or input referred noise are also provided with the corresponding simulation results.