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dc.contributorWalker, Duncan M.
dc.contributorChoi, Gwan
dc.creatorTamilarasan, Karthik Prabhu
dc.date.accessioned2012-02-14T22:18:53Z
dc.date.accessioned2012-02-16T16:13:39Z
dc.date.accessioned2017-04-07T19:59:04Z
dc.date.available2012-02-14T22:18:53Z
dc.date.available2012-02-16T16:13:39Z
dc.date.available2017-04-07T19:59:04Z
dc.date.created2010-12
dc.date.issued2012-02-14
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923
dc.description.abstractTesting of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.
dc.language.isoen_US
dc.subjectDelay test
dc.subjectsmall delay defects
dc.subjectweighted random pattern generation
dc.titleBuilt-In Self Test (BIST) for Realistic Delay Defects
dc.typeThesis


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