Suppressing Delta-I Noise In MCML Circuits In Mixed Signal Environment

This work addresses the problem of simultaneous switching noise (SSN) in mixed signal environment. It is shown that the Metal Oxide Semiconductor Current Mode Logic (MCML) can be used to minimize the SSN. In short channel devices, Drain Induced Barrier Lowering (DIBL) effect causes the current mismatch problem. It is seen that this current mismatch problem aggravates SSN. Basic logic gates were designed using MCML topology at 5 Gbps. Parasitic model was introduced at power supply lines and substrate to study the behaviour of these logic gates in the presence of parasitics. Interpolation type delay cells were used to suppress the detrimental effect of SSN caused by the parasitics in power supply lines and substrate of these MCML circuits. This allows us to introduce variable delays at input terminals. The results in this work show that the variable delay minimizes the current mismatch problem thus, suppressing SSN. The analysis of peak to peak noise amplitude at the output of MCML circuits with and without the delay cell illustrates that delay cells can be successfully employed to minimize current mismatch to reduce SSN. Delay cell increases the number of transistors which in turn adds to the complexity of the circuit. With the advancement in technology, new variable delay cells can be designed using less number of transistors, thus reducing the complexity.