Error Correction Methods For Latency-constrained Flash Memory Systems

Maintaining the reliability of data stored in Flash devices and reading it correctly has become a challenge as the demand for higher density is forcing aggressive shrinking of Flash architectures. For all Flash systems, especially latency-constrained NOR Flash, an on-chip error correction code (ECC) is the only viable and robust solution to this problem.
This thesis investigates and optimizes low-latency error correction schemes for on-chip implementation in NOR systems using existing error correction methods as a starting point. As the first step towards doing this, a mathematical relation has been derived to compute the bit error rate (BER) of a memory array using technology-specific voltage distribution curves. The required error correction capacity is calculated using the BER of the memory array. Current on-chip error correction (ECC) schemes in NOR Flash consist of a single error correcting Hamming code. However, for emerging Flash devices single bit error correction does not suffice to maintain data reliability. This problem has been addressed by analyzing and optimizing existing ECC schemes for low latency and minimal hardware and parity overhead while achieving at least 2-bit error correction. One of the proposed algorithms is a dual bit Hamming code which uses the Hamming code for 2-bit error detection and correction. Another optimized scheme, called Hierarchical BCH, makes effective use of the fast and simple Hamming code to correct frequently occurring single bit errors and the multi error correction BCH code to correct higher order errors in the rare case when the Hamming code detects a 2-bit error. This scheme gives an average latency of around 4ns while improving the array BER from from 10-7 to 10-15. Thus all these methods have been quantitatively proven to be applicable in latency-constrained eXecute-in-Place (XiP) NOR Flash systems.